Recent improvements of electronic circuitry with corresponding increases in speed of operation, has created a need for more efficient and faster testing systems. One method for increasing system efficiency and speed is to integrate as much of the system as possible into a single CMOS IC (integrated circuit). Such high-level integration increases speed and efficiency because signals have less distance to travel. A well-designed CMOS chip also increases noise immunity of internal signals.
Prior art test equipment systems must provide an interface from which to send and receive signals. Generally, this interface provides an output driver circuit for driving output signals onto an external line and a receiver circuit for receiving each signal coming from an external device. Typically, the receiver circuits used in a test equipment system must be able to operate in one of at least two modes. In a first mode, the receiver circuit must have the capability of operating in a transparent mode, whereby the data passed on to the test equipment system follows that of the incoming data. In a second mode, the receiver circuit must have the capability to detect whether any transition occurred on an incoming signal. The second mode, which may be called window compare mode, is useful for detecting glitches on a signal which should be constant over a long period of time. For example, if the incoming data signal received by the receiver circuit is a clock signal, window compare mode may be enabled to determine if a glitch occurred on the clock signal and unintentionally clocked another device. To accommodate these two modes, most typical prior art test systems include window latches in their receiver circuits which may operate in either transparent mode or window compare mode.
In a digital test system, a digital signal may assume any one of a defined number of levels, dependent only upon the degree of signal quantization used by the test system. For example, in a binary system, a digital signal represents a "zero" or a "one". FIG. 1 is a graphical illustration of the relationship in a binary digital circuit between the high reference voltage threshold, the low reference voltage threshold, and voltage levels recognized by the digital circuit with respect to these voltages. As shown in FIG. 1, a binary digital signal is detected as a "zero" or "one" when it comes within a defined voltage range which is delineated by defined voltage thresholds. Thus, as shown in FIG. 1, a "zero" is detected and said to be in a valid low state whenever the binary digital signal is below a low reference voltage threshold defined by VREFL. A "one" is likewise detected and said to be in a valid high state whenever the signal is above a high reference voltage threshold defined by VREFH. Using this simple voltage range recognition technique, digital circuit components easily classify an input signal as a "zero" or "one" when the signal is within either the range below the low reference voltage threshold VREFL or the range above the high reference voltage threshold VREFH. However, when the input signal is transitioning from one state to the other (i.e., when the input signal is above the low reference voltage threshold VREFL but below the high reference voltage threshold VREFH), the signal is in an intermediate state and said to be "floating". In the intermediate state, the level of the signal recognized by the digital circuit component is indeterminate. In a binary digital system, the specific voltage levels corresponding to the high reference voltage threshold VREFH and the low reference voltage threshold VREFL may both vary depending upon the family of components used or upon the specific application. For example, in transistor-transistor logic (TTL), a commonly used component family, the high reference voltage threshold may be +2.0 volts and the low reference voltage threshold may be +0.8 volts. Likewise, in CMOS components, the high reference voltage threshold may be 3.15 volts and the low reference voltage threshold may be 0.9 volts. For ECL components, the high reference voltage threshold may be -1.105 volts and the low reference voltage threshold may be -1.475 volts. FIG. 1 illustrates a signal in a binary system. Digital test systems, however, may be based on any number of different quantization levels, where each level is associated with a defined voltage range delineated by defined reference voltage thresholds.
FIG. 2 illustrates an example binary digital test system 10 connected to an external device under test (DUT) 20. As shown in FIG. 2, the DUT 20 receives input signals I[0]-I[m] from the test system 10 and provides output signals O[0]-O[n] which are received by the test system 10. As also shown in FIG. 2, the test system 10 generally includes an output driver circuit 18 for each of the input signals I[0]-I[m] generated by system circuitry 30 of the test system 10. The test system 10 also generally includes a receiver circuit 16 for each of the output signals O[0]-O[n] that are received from the DUT 20, decoded and sent to the system circuitry 30. Typical receiver circuits include a high level comparator 12 and a low level comparator 14, which may reside either internal or external (as shown in FIG. 2) to the receiver circuit 16. The high-level comparator 12 generally compares the output signal O[x], where x::0..n, received from the DUT 20 to a high reference voltage VREFH and outputs a high-level comparator signal HLC[x] for use by the receiver circuit 16. Similarly, the low-level comparator 14 generally compares the output signal O[x] received from the DUT 20 to a low reference voltage VREFL and outputs a low-level comparator signal LLC[x] for use by the receiver circuit 16. The defined polarity of each of the high-level comparator signal HLC[x] and the low-level comparator signal LLC[x] may depend on the implementation of the receiver circuit 16. For example, FIG. 3 illustrates a sample output signal O[x] which crosses the low reference voltage VREFL and the high reference voltage VREFH, in sequence starting from below VREFL, as follows: above VREFL, above VREFH, below VREFH, back above VREFH, back below VREFH, below VREFL, back above VREFL, back below VREFL, and back above VREFL. Typical receiver circuits expect the same polarity on both the respective high-level comparator signal HLC[x] and low-level comparator signal LLC[x] if the output signal O[x] is above the respective reference voltages VREFH and VREFL. In other words, when the output signal O[x] is above the low reference voltage VREFL, the low level comparator signal LLC[x] will be logically high (or logically low if the receiver circuit 16 is based on the opposite polarity), and when the output signal O[x] is above the high reference voltage VREFH, the high level comparator signal HLC[x] will be logically high (or logically low if the receiver circuit 16 is based on the opposite polarity). So, as shown in FIG. 3, the LLC[x] signal is a high polarity whenever the output signal O[x] crosses above the VREFL threshold, and the HLC[x] signal is a high polarity whenever the output signal O[x] crosses above the VREFH threshold. This is typical when using a similar type comparator for generating both the high-level compare signal HLC[x] and the low-level compare signal LLC[x]. As known by those skilled in the art, utilizing inverting comparators will generate HLC and LLC signals which are the inverted version of those shown in FIG. 3.
Alternatively, the receiver circuit 16 may require HLC[x] and LLC[x] signals which more closely map the location of the signal O[x]. This may be accomplished by utilizing an inverting comparator for the low-level comparator 14 while maintaining a non-inverting comparator for the high-level comparator 12, or vice versa. Thus, the LLC[x] signal shown in FIG. 4 is generated by an inverting comparator and the HLC[x] signal is generated by a non-inverting compartator. As shown in FIG. 4, for an identical output signal O[x] as that shown in FIG. 3, the use of an inverting comparator for low-level comparator 14 results in an LLC[x] signal which is the inverted version of the LLC[x] signal shown in FIG. 3, where a non-inverting comparator is used for low-level comparator 14. The benefit of utilizing an inverting and a non-inverting comparator to generate the LLC and HLC signals respectively as shown in FIG. 4, is that the HLC[x] signal is high (or "asserted") only when the output signal O[x] is valid high, and the LLC[x] signal is high (or "asserted") only when the output signal O[x] is valid low. This scheme simplifies the necessary decoding to determine whether the output signal O[x] is in a valid state or an intermediate state. Again, as known by those skilled in the art, the polarity of the HLC[x] and LLC[x] signals may be reversed if the receiver circuit 16 recognizes asserted low signals instead of asserted high signals. In this case, the high-level comparator 12 would be implemented with an inverting comparator and the low-level comparator 14 would be implemented with a non-inverting comparator.
Regardless of the definition of the polarities of each of the high-level compare signal HLC[x] and low-level compare signal LLC[x], the receiver circuit 16 typically generates a high data signal HD[x], a low data signal LD[x], and an intermediate data signal ID[x], each of which is asserted only when the output signal O[x] is in a respective high voltage range, intermediate voltage range, or low voltage range. Accordingly, only one data signal HD[x], LD[x], or ID[x], is asserted at any given time.
It is known in the art that electrical signals derived from the same source but traveling different paths, even when the paths are theoretically identical, may not arrive downstream at the same time. In other words, with reference to the test system 10 of FIG. 2, even though the high level comparator 12 and low level comparator 14 circuit elements may be identical, and the distance between the initial receipt of an output signal O[x] and the different inputs to the respective comparators 12 and 14 may be identical, the HLC[x] and LLC[x] signals may not switch with the exact delay as the other path. This is known as data skew. Data skew may be introduced by process variations in the fabrication of the circuit, component variations, or by design (typically where one electrical path is longer in distance than another). FIG. 5 is a timing diagram of the example output signal O[x] which shows the uncompensated high-level and low-level comparator signals HLC[x] and LLC[x] where the LLC signal path has a longer delay that the HLC path. For comparison, the ideal timing of the low-level comparator signal LLC[x] is also shown.
Conventional prior art receiver circuits which provide a window compare mode compensate for data skew by introducing delay elements into the data signal paths. FIG. 6 shows a typical prior art receiver circuit 60 which compensates for data skew. The receiver circuit 60 shown in FIG. 6 receives the high-level comparator signal HLC and low-level comparator signal LLC. The HLC signal and LLC signal are each delayed by respective delay elements 61 and 62. The respective delayed signals H and L are logically NOR'd together by OR gate 63 to produce an intermediate signal I. Each of the respective delayed high H, intermediate I, and delayed low L signals are then passed through respective window latches 64, 65, 66. The window latches may be enabled to operate in a window compare mode, which captures a transition from high-to-low or from low-to-high by the respective delayed high H, intermediate I, and delayed low L signals, at any time during which a window compare mode enable signal WIN.sub.-- EN is asserted (high). If the window latches are not enabled (i.e., if WIN.sub.-- EN is low), the window latches operate like transparent latches by simply passing the respective delayed high H, intermediate I, and delayed low L signals to their respective outputs. The window latches 64, 65, 66 produce respective window latch output signals H1, I1 and L1. The receiver circuit 60 also includes a set of edge-triggered flip-flops 67, 68 and 69. One edge-triggered flip-flop 67 receives window latch output signal H1; another edge-triggered flip-flop 68 receives window latch output signal I1; and another edge-triggered flip-flop 69 receives window latch output signal L1. Each of the edge-triggered flip-flops captures the state of its respective input signal H1, I1 and L1 as high data HD, intermediate data ID, and low data LD signals when an active edge of a clock signal CK occurs.
FIG. 7 is a timing diagram illustrating the timing of the prior art receiver circuit 60 of FIG. 6 in both the transparent latch mode (i.e., where signal WIN.sub.-- EN is low) and in window compare mode (i.e., where signal WIN.sub.-- EN is high). As shown in FIG. 7, if a clock occurred at time t1, and it captured the uncompensated HLC and LLC, it would appear that the incoming data signal DATA was both high and low at the same moment in time, which is not valid. The deskewed data has the proper timing relationships so that the clock correctly captures the data as a low at time t1 and an intermediate at time t1'. At time t2, the clock correctly captures the data such that the data was both high and intermediate during some period during the window compare mode (i.e., where WIN.sub.-- EN is asserted). As known by those skilled in the art, multiple values are valid when the receiver circuit is operating in window compare mode.
It will be appreciated by one skilled in the art that at a minimum the receiver circuit 60 will utilize one delay element to delay one or the other of the HLC or LLC signals. This is because one of the delay elements 61 or 62 may have a relative delay of zero, if it is known that one of the HLC or LLC paths is always longer, and thus is not needed. It will also be appreciated that the rest of the receiver circuit 60 of the prior art may be implemented in a variety of other ways; however, other prior art implementations generally utilize some type of delay element in the data path as shown in FIG. 6.
With the need for increased speed and efficiency in electrical test systems, it would be desirable from the standpoint of improving power consumption, cost and reliability to integrate more of the test system functionality into a CMOS chip. However, prior art receiver circuits such as that shown in FIG. 6 cannot be integrated into CMOS chips because the typical adjustable CMOS delay element may not have a high enough bandwidth (500 MHZ or more) for these signals, or may have only one precision edge (e.g., only the rising edge), and thus would not be suitable for delaying a data signal.